代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
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vhd vhdl code4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT
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bak vhdl code4.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT
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bak vhdl code7.bak
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
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vhd vhdl code7.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
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vhd vhdl code1.vhd
-- This is the VHDL code for the counter example from _The VHDL
-- Cookbook_ by Peter Ashenden. The propogation delay has been removed.
entity count2 is
port (clock : in bit; q1, q0 : out bit)
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bak vhdl code1.bak
-- This is the VHDL code for the counter example from _The VHDL
-- Cookbook_ by Peter Ashenden. The propogation delay has been removed.
entity count2 is
port (clock : in bit; q1, q0 : out bit)
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vhd vhdl code6.vhd
--Entity declaration for 4:1 Mux
ENTITY mux41 is
port( d0, d1, d2, d3 : in bit_vector;
s0, s1, en : in bit;
z : out bit_vector);
END ENTITY mux41;
--Architecture for 4:1 Mux
ARCHITECTURE beh
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bak vhdl code6.bak
--Entity declaration for 4:1 Mux
ENTITY mux41 is
port( d0, d1, d2, d3 : in bit_vector;
s0, s1, en : in bit;
z : out bit_vector);
END ENTITY mux41;
--Architecture for 4:1 Mux
ARCHITECTURE beh
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bak vhdl code8.bak
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi
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vhd vhdl code8.vhd
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi