vhdl code4.vhd

来自「d flip flop t flip flop counter mux usin」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='1') THEN Q<='0';QINV<='1';
ELSIF D='1' THEN Q<='1';QINV<='0';
ELSE Q<='0';QINV<='1';
END IF;
END PROCESS;
END behav;