代码搜索：SmartGen
找到约 50 项符合「SmartGen」的源代码
代码结果 50
www.eeworm.com/read/17603/740631
prj main_syn.prj
#add_file options
add_file -verilog "F:/Actel_prj/myprj/simple_beep/smartgen/PLL_25M/PLL_25M.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/key_measure.v"
add_file -verilog "F:/Actel_prj/
www.eeworm.com/read/457775/1593280
srd lcd_top.srd
f "noname"; #file 0
f "d:\libero\synplify\synplify_862h\lib\proasic\fusion.v"; #file 1
f "c:\actelprj\yan\lcd_1602\smartgen\pll_1m\pll_1m.v"; #file 2
f "c:\actelprj\yan\lcd_1602\hdl\clock_gen.v"; #
www.eeworm.com/read/457775/1593283
prj lcd_top_syn.prj
#add_file options
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project
www.eeworm.com/read/457775/1593287
sav lcd_top_syn.prj.convert.sav
#add_file options
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project
www.eeworm.com/read/409884/11308315
prj pll_top_syn.prj
#add_file options
add_file -verilog "D:/Actelprj/Static_PLL/hdl/ctrl_PLL.v"
add_file -verilog "D:/Actelprj/Static_PLL/smartgen/PLL_0P75M/PLL_0P75M.v"
add_file -verilog "D:/Actelprj/Static_PLL/hdl/P
www.eeworm.com/read/17603/740654
srd main.srd
f "noname"; #file 0
f "c:\actel\libero8.0\synplify\synplify_88a1\lib\proasic\fusion.v"; #file 1
f "f:\actel_prj\myprj\simple_beep\smartgen\pll_25m\pll_25m.v"; #file 2
f "f:\actel_prj\myprj\simple_b
www.eeworm.com/read/18154/777261
srd fpga_core.srd
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v"; #file 2
f "h:\fpga_test\fpga_
www.eeworm.com/read/315669/13538554
srd cmos_fifo_usb.srd
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v"; #file 2
f "h:\fpga_test\cmos_fifo_u
www.eeworm.com/read/492682/6418932
prj lcd_top_syn.prj
#add_file options
add_file -verilog "E:/1/2/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "E:/1/2/LCD实验/Project/LCD_1602/hdl/Clock_Gen.v"
add_file -verilog "E:/1/2/LCD实验/Projec
www.eeworm.com/read/18154/777260
prj fpga_core_syn.prj
#add_file options
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v"
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v"
#device o