pll_top_syn.prj

静态pll实验程序

#add_file options
add_file -verilog "D:/Actelprj/Static_PLL/hdl/ctrl_PLL.v"
add_file -verilog "D:/Actelprj/Static_PLL/smartgen/PLL_0P75M/PLL_0P75M.v"
add_file -verilog "D:/Actelprj/Static_PLL/hdl/PLL_top.v"
set_option -top_module PLL_top

#device options
set_option -technology Fusion
set_option -part AFS600
set_option -vlog_std v2001

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "D:/Actelprj/Static_PLL/synthesis/PLL_top.edn"