lcd_top_syn.prj

基于FPGA的LCD1602驱动

#add_file options
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/hdl/Clock_Gen.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/hdl/LCD_Driver.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/hdl/LCD_Top.v"
set_option -top_module LCD_Top

#device options
set_option -technology Fusion
set_option -part AFS600
set_option -vlog_std v2001

KEY LIBERO "8.4"
KEY CAPTURE "8.4.0.33"
KEY DEFAULT_IMPORT_LOC "E:\实验例程\LCD实验例程\Source File"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family ""
KEY VendorTechnology_Die ""
KEY VendorTechnology_Package ""
KEY ProjectLocation "F:\FPGA大赛\FUSION STARTKIT (G)\实验例程\高级实验\LCD实验\Project\LCD_1602\synthesis"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST FileManager
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=coreconsole
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=F:\Libero\Libero_v8.4\Synplify\synplify_94A1\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=F:\Libero\Libero_v8.4\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=F:\Libero\Libero_v8.4\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=F:\Libero\Libero_v8.4\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
ACTIVE_VIEW:0
ENDLIST
impl -active "synthesis"
project -result_file "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/synthesis/LCD_Top.edn"