fpga_core_syn.prj

来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· PRJ 代码 · 共 20 行

#add_file options
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v"
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v"

#device options
set_option -technology ProASIC3
set_option -part A3P125
set_option -vlog_std v2001
set_option -disable_io_insertion 1

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "H:/fpga_test/fpga_fifo_0122_02/synthesis/fpga_core.edn"