main_syn.prj

基于FPGA的VHDL编程实现各种音频信号

#add_file options
add_file -verilog "F:/Actel_prj/myprj/simple_beep/smartgen/PLL_25M/PLL_25M.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/key_measure.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_simple_beep.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_note_A_440HZ.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_440HZ.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_parameter.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_ambulance_siren.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/divide_by12.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_tune.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_police_siren.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/music_high_speed_pursuit.v"
add_file -verilog "F:/Actel_prj/myprj/simple_beep/hdl/main.v"

#device options
set_option -technology Fusion
set_option -part AFS600
set_option -vlog_std v2001




#implementation: "synthesis"
impl -add synthesis -type fpga

set_option -package ""
set_option -speed_grade -1
#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0

#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"

#
#implementation attributes

impl -active "synthesis"
project -result_file "F:/Actel_prj/myprj/simple_beep/synthesis/main.edn"