代码搜索：SmartGen

找到约 50 项符合「SmartGen」的源代码

代码结果 50
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/18154/777192

aws smartgen.aws

smartgenVerilog
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www.eeworm.com/read/457775/1593260

aws smartgen.aws

smartgenVerilog
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www.eeworm.com/read/299888/3849674

aws smartgen.aws

smartgenVerilog
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www.eeworm.com/read/471689/6888112

aws smartgen.aws

smartgenVHDL
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www.eeworm.com/read/492682/6418903

gen pll_1m.gen

Version:8.0.1.13 ACTGENU_CALL:1 BATCH:T FAM:Fusion OUTFORMAT:Verilog LPMTYPE:LPM_PLL_STATIC LPM_HINT:NONE INSERT_PAD:NO INSERT_IOREG:NO GEN_BHV_VHDL_VAL:F GEN_BHV_VERILOG_VAL:F MGNTIMER:F
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www.eeworm.com/read/409884/11308262

gen pll_0p75m.gen

Version:8.4.0.33 ACTGENU_CALL:1 BATCH:T FAM:Fusion OUTFORMAT:Verilog LPMTYPE:LPM_PLL_STATIC LPM_HINT:NONE INSERT_PAD:NO INSERT_IOREG:NO GEN_BHV_VHDL_VAL:F GEN_BHV_VERILOG_VAL:F MGNTIMER:F
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www.eeworm.com/read/409880/11308397

gen pll_1m.gen

Version:8.4.0.33 ACTGENU_CALL:1 BATCH:T FAM:Fusion OUTFORMAT:Verilog LPMTYPE:LPM_PLL_STATIC LPM_HINT:NONE INSERT_PAD:NO INSERT_IOREG:NO GEN_BHV_VHDL_VAL:F GEN_BHV_VERILOG_VAL:F MGNTIMER:F
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www.eeworm.com/read/315669/13538547

prj cmos_fifo_usb.prj

KEY LIBERO "8.0" KEY CAPTURE "8.0.0.40" KEY DEFAULT_IMPORT_LOC "F:\FPGA_TOP0415\hdl" KEY DEFAULT_OPEN_LOC "C:\Documents and Settings\Administrator\桌面" KEY HDLTechnology "VERILOG" KEY VendorTechno
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www.eeworm.com/read/315669/13538565

srr cmos_fifo_usb.srr

#Build: Synplify 8.8A1, Build 015R, Apr 16 2007 #install: C:\acter\Libero\Synplify\Synplify_88A1 #OS: Windows XP 5.1 #Hostname: PRIMAX-142F7BC7 #Implementation: synthesis #Tue May 20 23:22:02
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www.eeworm.com/read/315669/13538550

prj cmos_fifo_usb_syn.prj

#add_file options add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/two_port1280x8/two_port1280x8.v" add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/usb_fifo32x16/usb_fifo32x16.v" add_f
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