pll_1m.gen

液晶屏lcd1602的使用历程

Version:8.4.0.33
ACTGENU_CALL:1
BATCH:T
FAM:Fusion
OUTFORMAT:Verilog
LPMTYPE:LPM_PLL_STATIC
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:D:/Actelprj/LCD_1602/smartgen\PLL_1M
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IR6X6M2
SMARTGEN_PACKAGE:fg256
FIN:48.000000
CLKASRC:1
FBDLY:1
FBMUX:1
XDLYSEL:0
PRIMFREQ:1.000000
PPHASESHIFT:0
DLYAVAL:1
OAMUX:4
POWERDOWN_POLARITY:0
LOCK_POLARITY:1
LOCK_CTL:0