cmos_fifo_usb.prj

cmos数据到fifo再到usb的fifo部分程序(68013a)

KEY LIBERO "8.0"
KEY CAPTURE "8.0.0.40"
KEY DEFAULT_IMPORT_LOC "F:\FPGA_TOP0415\hdl"
KEY DEFAULT_OPEN_LOC "C:\Documents and Settings\Administrator\桌面"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "IS2X2M1"
KEY VendorTechnology_Package "vq100"
KEY ProjectLocation "H:\fpga_test\cmos_fifo_usb"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "cmos_fifo_usb::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\hdl\cmos_fifo.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8.log,log"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8.v,hdl"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R1C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
ENDFILE
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R2C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\two_port1280x8\two_port1280x8.cxf"
ENDFILE
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\usb_fifo32x16\usb_fifo32x16.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16.log,log"
STATE="utd"
PARENT="<project>\smartgen\usb_fifo32x16\usb_fifo32x16.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16.v,hdl"
STATE="utd"
PARENT="<project>\smartgen\usb_fifo32x16\usb_fifo32x16.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\usb_fifo32x16\usb_fifo32x16.cxf"
ENDFILE
VALUE "<project>\stimulus\cmos_fifo_tb.v,tb_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\cmos_fifo_usb.edn,syn_edn"
STATE="ood"
ENDFILE
VALUE "<project>\synthesis\cmos_fifo_usb_sdc.sdc,syn_sdc"
STATE="ood"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST AssociatedStimulus
LIST cmos_fifo_usb
VALUE "<project>\stimulus\cmos_fifo_tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST two_port1280x8
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R0C0.mem,sim"
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R1C0.mem,sim"
VALUE "<project>\smartgen\two_port1280x8\two_port1280x8_R2C0.mem,sim"
ENDLIST
LIST usb_fifo32x16
VALUE "<project>\smartgen\usb_fifo32x16\usb_fifo32x16_R0C0.mem,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
CompilePackage=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=cmos_fifo_tb
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=C:\CoreConsole_v1.3\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=C:\Libero\Synplify\Synplify_88A1\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=PALACE
Tool=PALACE
Location=palace_actel.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=C:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "cmos_fifo_usb::work"
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\cmos_fifo_usb.edn,syn_edn"
VALUE "<project>\synthesis\cmos_fifo_usb_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\cmos_fifo_usb.v,syn_hdl"
VALUE "<project>\phy_synthesis\cmos_fifo_usb_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\cmos_fifo_usb_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\cmos_fifo_usb_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\cmos_fifo_usb_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\cmos_fifo_usb_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\cmos_fifo_usb.adb,adb"
VALUE "<project>\designer\impl1\cmos_fifo_usb.prb,prb"
VALUE "<project>\designer\impl1\cmos_fifo_usb.stp,stp"
VALUE "<project>\designer\impl1\cmos_fifo_usb_fp\cmos_fifo_usb.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\hdl\cmos_fifo.v,hdl
FILE:<project>\stimulus\cmos_fifo_tb.v,tb_hdl
ACTIVE_VIEW:1
ENDLIST