代码搜索：SOUT
找到约 712 项符合「SOUT」的源代码
代码结果 712
www.eeworm.com/read/424814/10410192
v transmit_test.v
//Test Case 1
//UART Tx test: 5/6/7/8 bit, even/odd parity, parity/non-parity/stick parity, 1/1.5/2 stop bit
wire [7:0] golden_data1 = 8'b01010101;//55
wire [7:0] golden_data2 = 8'b10101010
www.eeworm.com/read/146459/7215522
v txblock.v
//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003
www.eeworm.com/read/320591/13422574
vhd compare.vhd
--function : compare data
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare is
port(
sin1 : in std_logic;
sin2 : in std_logic;
clk1 : in std_logic
www.eeworm.com/read/125531/6028063
java attachmentmanagertest.java
package com.ecyrd.jspwiki.attachment;
import junit.framework.*;
import java.io.*;
import java.util.*;
import com.ecyrd.jspwiki.*;
import com.ecyrd.jspwiki.providers.*;
public class AttachmentManag
www.eeworm.com/read/108123/6185844
java attachmentmanagertest.java
package com.ecyrd.jspwiki.attachment;
import junit.framework.*;
import java.io.*;
import java.util.*;
import com.ecyrd.jspwiki.*;
import com.ecyrd.jspwiki.providers.*;
public class AttachmentManag
www.eeworm.com/read/130952/14166443
cpp view.cpp
// MiniFTP copyright 1997 Paul Gerhart pgerhart@voicenet.com
// View.cpp : implementation of the CMiniFTPView class
//
// search for.... // THIS IS WHERE THIS APP REALLY STARTS
#include "std
www.eeworm.com/read/472423/6867394
vhd add8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADD8 IS
PORT(
CIN : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWN
www.eeworm.com/read/135521/13924276
vhd adder_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_2 is
port(dataa : in std_logic_vector(17 downto 0);
datab : in std_logic_vector(17 downto 0);
www.eeworm.com/read/135521/13924279
vhd adder_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_4 is
port(dataa : in std_logic_vector(19 downto 0);
datab : in std_logic_vector(19 downto 0);
www.eeworm.com/read/135521/13924287
vhd adder_8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_8 is
port(dataa : in std_logic_vector(23 downto 0);
datab : in std_logic_vector(23 downto 0);