add8.vhd

几个VHDL实现的源程序及其代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADD8 IS
PORT(
CIN :  IN STD_LOGIC;
A   :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B   :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT: OUT STD_LOGIC);
END ADD8;

ARCHITECTURE STRUC OF ADD8 IS
COMPONENT ADD4
PORT(
CIN : IN STD_LOGIC;
A   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END COMPONENT;
SIGNAL CARRY_OUT : STD_LOGIC;
SIGNAL SOUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
S<=SOUT;
U1: ADD4 PORT MAP(CIN=>CIN,A=>A(3 DOWNTO 0),B=>B(3 DOWNTO 0),S=>SOUT(3 DOWNTO 0),COUT=>CARRY_OUT);
U2: ADD4 PORT MAP(CIN=>CARRY_OUT,A=>A(7 DOWNTO 4),B=>B(7 DOWNTO 4),S=>SOUT(7 DOWNTO 4),COUT=>COUT);
END STRUC;