adder_2.vhd

来自「自已写的一个16X16的乘法器」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder_2 is  
  port(dataa : in std_logic_vector(17 downto 0);
       datab : in std_logic_vector(17 downto 0);
       sout : out std_logic_vector(19 downto 0));
end adder_2;

architecture arc of adder_2 is
begin
  sout <= ("00" & dataa) + ( datab & "00");
end arc;