compare.vhd

ppm脉位调制数字基带系统的设计

--function : compare data
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity compare is
port(
	sin1 : in std_logic;
	sin2 : in std_logic;
	clk1 : in std_logic;
	clk2 : in std_logic;
	sout : out std_logic
	);
end compare;

architecture behave of compare is
signal tmp1 : std_logic;
signal tmp2 : std_logic;
begin
	process(sin1,sin2,clk1,clk2)
	begin
		tmp1 <= sin1 xor clk1;
		tmp2 <= sin2 xor clk2;
		if tmp1 = '0' and tmp2 = '0' then
			sout <= not tmp1;
		else
			sout <= '0';
		end if;
	end process;
end behave;