txblock.v

专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550

//////////////////////////////////////////////////////////////////////////////////////////////
//
//----------------------------------------------------------------------
//
// Copyright (c) 2002-2003 CAST, inc.
//
// Please review the terms of the license agreement before using this
// file.  If you are not an authorized user, please destroy this source
// code file and notify CAST immediately that you inadvertently received
// an unauthorized copy.
//----------------------------------------------------------------------
//
//  Project       : H16550 UART
//
//  File          : txblock.v
//
//  Dependencies  : none 
//
//  Model Type    : Synthesizable Core
//
//  Description   : Transceiver block
//
//  Designer      : JU
//
//  QA Engineer   : JH
//
//  Creation Date : 02-January-2002
//
//  Last Update   : 20-June-2003
//
//  Version       : 2.0V
//
//  History       : 1.1 - 02/18/02    VHDL Release
//                  1.2 - 04/16/02    Performance (size) improved
//                  1.3 - 01/29/03    Thrint1 bug fixed 
//                  2.0 - 06/20/03    Add THRE indication delay time
//
//----------------------------------------------------------------------

`timescale 1 ns/1 ps

module txblock (clk, mr, txbaud, txfifo_empty, txfifo_2char, fcreg_b0, lsreg_b5, thrint, lcreg, threg, thrint1, temt, read_txfifo, sout_org);

   `include "h16550_params.v"

   input clk; // System Clock
   input mr; // Master Reset
   input txbaud; // Transmitter Baud
   input txfifo_empty; // Transmitter Fifo Empty flag
   input txfifo_2char; // Transmitter fifo has 2 chars
   input fcreg_b0; // Fifo enable
   input lsreg_b5; // Transmitter holding register empty status
   input thrint; // Transmitter Holding Register Empty interrupt
   input[6:0] lcreg; // Line Control register
   input[DATA_WIDTH - 1:0] threg; // Transmitter holding register
   output thrint1; // Transmitter Holding Register Empty interrupt1
   wire thrint1;
   output temt; // Transmitter Fifo empty
   reg temt;
   output read_txfifo; // Read Transmitter fifo enable
   wire read_txfifo;
   output sout_org; 
   wire sout_org;

   reg[4:0] state; 
   reg[4:0] next_state; 
   reg[DATA_WIDTH - 1:0] tsreg; 
   reg parity; 
   reg break; 
   reg sout_bit; 
   reg sout_int; 
   reg temt1; 
   reg thrint1_int; 
   reg parity_lcreg4; 
   reg invert_parity; 
   reg read_txfifo_int; 
   reg delay_read_txfifo; 
   reg tx_2char_event; 
   reg stop_bit_tx_rupt; 

   assign thrint1 = thrint1_int ; 
   assign sout_org = sout_int ; 
   assign read_txfifo = read_txfifo_int ; 

   //--------------------------------------------------
   // Force SOUT to ZERO when there is break condition 
   //--------------------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         sout_int <= 1'b1 ; 
      end
      else
      begin
         if (break == 1'b1)
         begin
            sout_int <= 1'b0 ; 
         end
         else
         begin
            if (txbaud == 1'b1)
            begin
               sout_int <= sout_bit ; 
            end 
         end 
      end 
   end 

   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         break <= 1'b0 ; 
      end
      else
      begin
         break <= lcreg[6] ; 
      end 
   end 

   //---------------------
   // TEMT bit generation 
   //---------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         temt <= 1'b1 ; 
      end
      else
      begin
         if (txbaud == 1'b1 & txfifo_empty == 1'b1 & temt1 == 1'b1)
         begin
            temt <= 1'b1 ; 
         end 
         if (txfifo_empty == 1'b0)
         begin
            temt <= 1'b0 ; 
         end 
      end 
   end 

   // For fifo mode, the transmitter FIFO empty indications will be delayed 1 character time
   // minus the last stop bit time whenever the following occurs: THRE = 1 and
   // there have not been at least 2 bytes at the same time in the transmit FIFO, since
   // the last THRE = 1
   // If only one character is loaded to fifo, the interrupt occurs at the end of
   // the character

   always @(posedge clk or posedge mr)
   begin
      if (mr == 1'b1)
      begin
         thrint1_int <= 1'b1 ; 
      end
      else
      begin
         // Transmitter Holding Register Empty Interrupt
         //if (state = SEND_START1 and thrint = \'0\' and txfifo_empty = \'1\') then
         //if (delay_read_txfifo = \'1\' and thrint = \'0\' and txfifo_empty = \'1\') then
         if ((delay_read_txfifo == 1'b1 & thrint == 1'b0 & txfifo_empty == 1'b1) & (tx_2char_event == 1'b1 | fcreg_b0 == 1'b0))
         begin
            thrint1_int <= ~thrint1_int ; 
         end
         else if (state == SEND1_STOP0 & thrint == 1'b0 & txfifo_empty == 1'b1 & stop_bit_tx_rupt == 1'b1)
         begin
            thrint1_int <= ~thrint1_int ; 
         end 
      end 
   end 

   always @(posedge clk or posedge mr)
   begin
      if (mr == 1'b1)
      begin
         tx_2char_event <= 1'b0 ; 
      end
      else
      begin
         if (txfifo_2char == 1'b1 & lsreg_b5 == 1'b0)
         begin
            tx_2char_event <= 1'b1 ; 
         end
         else if (lsreg_b5 == 1'b1)
         begin
            // THRE=1
            tx_2char_event <= 1'b0 ; 
         end 
      end 
   end 

   always @(posedge clk or posedge mr)
   begin
      if (mr == 1'b1)
      begin
         stop_bit_tx_rupt <= 1'b0 ; 
      end
      else
      begin
         if ((delay_read_txfifo == 1'b1 & thrint == 1'b0 & txfifo_empty == 1'b1) & (tx_2char_event == 1'b0 & fcreg_b0 == 1'b1))
         begin
            stop_bit_tx_rupt <= 1'b1 ; 
         end
         else if ((state == SEND1_STOP0 & thrint == 1'b0 & txfifo_empty == 1'b1 & stop_bit_tx_rupt == 1'b1) | (state == SEND1_STOP0 & stop_bit_tx_rupt == 1'b1))
         begin
            stop_bit_tx_rupt <= 1'b0 ; 
         end 
      end 
   end 

   always @(posedge clk)
   begin
      delay_read_txfifo <= read_txfifo_int ; 
   end 

   //------------------------------------------
   // Read Transmitter Holding Register Enable
   //------------------------------------------
   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         tsreg <= {1{1'b0}} ; 
         read_txfifo_int <= 1'b0 ; 
      end
      else
      begin
         read_txfifo_int <= 1'b0 ; 
         if (txbaud == 1'b1)
         begin
            if (((state == WAITING1 | state == SEND2_STOP1) & txfifo_empty == 1'b0) | (state == SEND2_STOP0 & txfifo_empty == 1'b0 & (lcreg[2]) == 1'b0))
            begin
               // SEND_START
               // 1 STOP BIT
               tsreg <= threg ; 
               read_txfifo_int <= 1'b1 ; 
            end 
         end 
      end 
   end 

   always @(posedge mr or posedge clk)
   begin
      if (mr == 1'b1)
      begin
         parity <= 1'b0 ; 
      end
      else
      begin
         if (txbaud == 1'b1)
         begin
            if (parity_lcreg4 == 1'b1)
            begin
               parity <= ~lcreg[4] ; 
            end 
            if (invert_parity == 1'b1)
            begin
               parity <= ~parity ; 
            end 
         end 
      end 
   end 

   //---------------------------
   // STATE MACHINE
   //---------------------------
   always @(posedge clk or posedge mr)
   begin : state_process
      if (mr == 1'b1)
      begin
         state <= WAITING1 ; 
      end
      else
      begin
         if (txbaud == 1'b1)
         begin
            state <= next_state ; 
         end 
      end 
   end