代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/102471/15780248
vhd sys_int.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
library UNISIM;
--use UNISIM.vcomponents.all;
entity sys_int is
generic (
ADDR_MSB : integer := 31;
DATA_MSB : integer := 31;
C
www.eeworm.com/read/291235/8433669
cpp rofunc.cpp
#include
#include
#include "nr.h"
using namespace std;
extern DP aa,abdevt;
extern const Vec_DP *xt_p,*yt_p;
DP NR::rofunc(const DP b)
{
const DP EPS=numeric_limits::
www.eeworm.com/read/390049/8488485
vhd pcm1770.vhd
--PCM1770.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PCM1770 is
port(rst_n : in std_logic;
DcWord : in std_logic_vector(23 downto 0);
adc
www.eeworm.com/read/286093/8788741
vhf top.vhf
-- VHDL model created from top.sch - Wed Jun 20 18:35:50 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcompo
www.eeworm.com/read/281822/9131754
js common.js
// 将一个变量转换为对象
function var_to_obj(val)
{
this.value=val;
}
// 判断是否大于某个数
function is_greater(field,crit,limit)
{
var Ret = (is_numeric(field,-1) ) ? (field.value > limit ) : false;
if (!Re
www.eeworm.com/read/372476/9509018
vhd cpu.vhd
--实验11 组合逻辑控制器实验
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
USE WORK.CPU_DEFS.ALL;
ENTITY CPU IS
PORT( clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
www.eeworm.com/read/371615/9545932
vhd pwm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
port(
clk,reset:in std_logic;
w:in std_logic_vector(3 downto 0);
pwm_pulse:out std_logic
);
end
www.eeworm.com/read/366699/9802148
vhd pn_gen.vhd
library IEEE;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;
LIBRARY altera
www.eeworm.com/read/363304/9960194
vhd count_money.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count_money is
port( clkin : in std_logic;
dip :