pcm1770.vhd

24位AD PCM1770的VHDL控制模块

--PCM1770.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PCM1770 is
port(rst_n    : in std_logic;
     DcWord   : in std_logic_vector(23 downto 0);
     adc_bck  : in std_logic;
     adc_lrclk: in std_logic;
     pd_n     :out std_logic;
     bck      :out std_logic;
     data     :out std_logic;
     lrclk    :out std_logic;
     ms_n     :out std_logic;
     mc       :inout std_logic;
     md       :out std_logic);
end PCM1770;

architecture rtl of PCM1770 is
  constant register_03:std_logic_vector:="0000001110000001";
  signal reg_dcword:std_logic_vector(63 downto 0);
  signal cnt: integer range 1 to 35;
  signal dnt: integer range 1 to 17;
  signal bcnt:  integer range 1 to 34;
begin
  process (adc_bck,rst_n)
  begin
    if (adc_bck'event and adc_bck='1') then
       if rst_n='0' then
          cnt <= 1;
	      ms_n <='1';	
	      mc <= '1';
	   elsif (cnt > 34) then
		      cnt <= 35;
       else
		      cnt <= cnt +1;
		      case cnt is
                  when  1|34 =>	ms_n <= '1';
		          when others=> ms_n <='0';
                                mc <= not mc;
		      end case;
      end if;
    end if;	 
  end process;
  
  process (mc,rst_n)
  begin
    if rst_n='0' then
	      md<='1';
          dnt <= 1;
    elsif (mc'event and mc='0') then
          dnt<=dnt+1;
	      md<=register_03(15-dnt+1);
    end if;
  end process;
  
  process (adc_bck)
  begin
    if (adc_bck'event and adc_bck='1') then
	    if (adc_lrclk = '1') then
		    bcnt <= 1;
	    else
		    bcnt <= bcnt + 1;
        end if;
	end if;
  end process;	
  
  process (adc_bck)
  begin
    if (adc_bck'event and adc_bck='0') then
	  if(cnt = 35) then
	    if( bcnt=2 ) then
			reg_dcword <= DcWord & "00000000" & DcWord & "00000000";
			data <= reg_dcword(63);
		else
			reg_dcword <= to_stdlogicvector(to_bitvector(reg_dcword) sll 1);
			data <= reg_dcword(63);
		end if;	
	  else
		reg_dcword <= (others=>'0');
	  end if;	
	end if;	
  end process;

pd_n <= rst_n;
bck  <= adc_bck;
lrclk <= adc_lrclk;  

end rtl;