pn_gen.vhd

一个PN序列发生器

library IEEE;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

LIBRARY lpm; 
USE lpm.lpm_components.all; 

LIBRARY altera;
USE altera.maxplus2.ALL;

ENTITY PN_GEN IS
  --  GENERIC(
  --        );
	PORT
	(
		clkin 	: IN STD_LOGIC;      --39.3216MHz
		reset	: IN STD_LOGIC;
		clkout	: OUT STD_LOGIC;
		PN_i	: OUT STD_LOGIC;
		PN_q	: OUT STD_LOGIC
		
		

     );
	
END PN_GEN;

ARCHITECTURE arch OF PN_GEN IS

signal counter_i	: std_logic_vector (4 downto 0):="00000";
signal counter_q	: std_logic_vector (4 downto 0):="00000";
signal ai		: std_logic_vector (14 downto 0):="000000000000001";
signal aq		: std_logic_vector (14 downto 0):="000000000000001";
signal ci		: std_logic_vector (15 downto 0):="1010001110100001";
signal cq		: std_logic_vector (15 downto 0):="1010001110100001";
signal ai_m		: std_logic;
signal aq_m		: std_logic;
signal state	: std_logic;
signal clk_div32: std_logic;
signal counter_div	: std_logic_vector (4 downto 0):="00000";
--signal clk_4d	: std_logic;
--signal clk_8d	: std_logic;
--signal clk_16d	: std_logic;
--signal clk_32d	: std_logic;
signal sysclk	: std_logic;
signal shift_en_i	: std_logic;
signal shift_en_q	: std_logic;
signal sumi		: std_logic_vector (2 downto 0);
signal sumq		: std_logic_vector (3 downto 0);
signal b0,b1,b2,b3,b4,b5	: std_logic_vector (1 downto 0);
signal bq0,bq1,bq2,bq3,bq4,bq5,bq6,bq7	: std_logic_vector (1 downto 0);
signal ai_dcom		: std_logic_vector (1 downto 0);
signal aq_dcom		: std_logic_vector (1 downto 0);	
signal reset_m		: std_logic;
signal reset_sig	: std_logic;

--component div_32_syn
-- PORT
--	(	clkin 	: IN STD_LOGIC;      --39.3216MHz
--		reset	: IN STD_LOGIC;
--		clkout	: OUT STD_LOGIC);
--END component;									
              										 
BEGIN

process(clkin)
begin
	if clkin 'event and clkin='0' then
		if(reset = '0') then
			counter_div <= "00000";
		else if(counter_div="11111") then
				counter_div <= "00000";
			else
				counter_div <= counter_div + 1;
			end if;
		end if;
	end if;
end process;
--********************************************--
process(clkin)
begin
	if clkin 'event and clkin='1' then
		case counter_div is
			when "00001" => clk_div32 <= '1';
			when others  => clk_div32 <= '0';
		end case;
	end if;
end process;
--********************************************--
--process(clkin)
--begin
--	if clkin 'event and clkin='1' then
--		clk_2d<= not clk_2d;
--	end if;
--end process;

--process(clk_2d)
--begin
--	if clk_2d 'event and clk_2d='1' then
--		clk_4d<= not clk_4d;
--	end if;
--end process;

--process(clk_4d)
--begin
--	if clk_4d 'event and clk_4d='1' then
--		clk_8d<= not clk_8d;
--	end if;
--end process;

--process(clk_8d)
--begin
--	if clk_8d 'event and clk_8d='1' then
--		clk_16d<= not clk_16d;
--	end if;
--end process;

--process(clk_16d)
--begin
--	if clk_16d 'event and clk_16d='1' then
--		clk_32d<= not clk_32d;
--	end if;
--end process;
--div1:div_32_syn port map(	clkin => clkin,
--							reset => reset,
--							clkout=> clk_div32
--						);


sysclk <= clk_div32;
clkout <= not sysclk;

--********************************************--

process(clkin)
begin
	if clkin 'event and clkin='0' then
		reset_m<=reset;
	end if;
end process;

process(clkin)
begin
	if clkin 'event and clkin='0' then
		reset_sig<=reset and (not reset_m);
	end if;
end process;

--********************************************--

--********************************************--
process(sysclk)
begin
	if sysclk 'event and sysclk='1' then
		ai_m<= ai(0);
	end if;
end process;

process(sysclk)
begin
	if sysclk 'event and sysclk='0' then
		ai_dcom <= ai_m & ai(0);
		if(counter_i=14) then
			shift_en_i <= '0';
		else
			shift_en_i <= '1';
		end if;
	end if;
end process;

process(sysclk)
begin
	if sysclk 'event and sysclk='1' then
		case (ai_dcom) is
			when "01" =>  state <='0';	counter_i <= "00000";
			when "11" =>  state <='0';	counter_i <= "00000";
			when "10" =>  state <='1';	counter_i <= "00001";
			when "00" =>  state <='1';	counter_i <= counter_i + 1;
			when others => null;
		end case;
	end if;
end process;

b0	<="0"&ai(0);
b1	<="0"&ai(2);
b2	<="0"&ai(6);
b3	<="0"&ai(7);
b4	<="0"&ai(8);
b5	<="0"&ai(10);

--b0	<="0"&ai(0);
--b1	<="0"&ai(5);
--b2	<="0"&ai(7);
--b3	<="0"&ai(8);
--b4	<="0"&ai(9);
--b5	<="0"&ai(13);


sumi <= (b0(1) & b0) +(b1(1) & b1) +(b2(1) & b2)+(b3(1) & b3)+(b4(1) & b4)+(b5(1) & b5);

process(sysclk)
begin
	if sysclk 'event and sysclk ='1' then
	 case shift_en_i is
		when '1'  => if(reset_sig = '1') then
						ai <= "000000000000001";
						PN_i <= ai(0); 
					 else
						PN_i <= ai(0); 
						ai(14) <= sumi(0);
						ai(13 downto 0) <= ai(14 downto 1);
					 end if;
		when '0'  => if(reset_sig = '1') then
						ai <= "000000000000001";
						PN_i <= ai(0); 
					 else
						PN_i <= '0'; 
						ai(14) <= ai(14);
						ai(13 downto 0) <= ai(13 downto 0);
					 end if;
		when others => null;
	end case;
	end if;
end process;
---------------------------------------------------------------

process(sysclk)
begin
	if sysclk 'event and sysclk='1' then
		aq_m<= aq(0);
--		ai_dcom <= ai_m(0) & ai(0);
	end if;
end process;

process(sysclk)
begin
	if sysclk 'event and sysclk='0' then
		--ai_m<= ai(0);
		aq_dcom <= aq_m & aq(0);
		if(counter_q=14) then
			shift_en_q <= '0';
		else
			shift_en_q <= '1';
		end if;
	end if;
end process;

process(sysclk)
begin
	if sysclk 'event and sysclk='1' then
		case (aq_dcom) is
			when "01" => 	counter_q <= "00000";
			when "11" =>  	counter_q <= "00000";
			when "10" =>  	counter_q <= "00001";
			when "00" =>  	counter_q <= counter_q + 1;
			when others => null;
		end case;
	end if;
end process;

bq0	<="0"&aq(0);
bq1	<="0"&aq(3);
bq2	<="0"&aq(4);
bq3	<="0"&aq(5);
bq4	<="0"&aq(9);
bq5	<="0"&aq(10);
bq6	<="0"&aq(11);
bq7	<="0"&aq(12);

sumq <= (bq0(1) & bq0(1) & bq0) +(bq1(1) &bq1(1) & bq1) +(bq2(1) &bq2(1) & bq2) +(bq3(1) & bq3(1) & bq3) +(bq4(1) &bq4(1) & bq4) +(bq5(1) &bq5(1) & bq5) +(bq6(1) &bq6(1) & bq6) +(bq7(1) & bq7(1) & bq7);

process(sysclk)
begin
	if sysclk 'event and sysclk ='1' then
	 case shift_en_q is
		when '1'  => if(reset_sig = '1') then
						aq <= "000000000000001";
						PN_q <= aq(0); 
					 else
						PN_q <= aq(0); 
						aq(14) <= sumq(0);
						aq(13 downto 0) <= aq(14 downto 1);
					 end if;
		when '0'  => if(reset_sig = '1') then
						aq <= "000000000000001";
						PN_q <= aq(0); 
					 else
						PN_q <= '0'; 
						aq(14) <= aq(14);
						aq(13 downto 0) <= aq(13 downto 0);
					 end if;
		when others => null;
	end case;
	end if;
end process;


		

END arch;