📄 count_money.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count_money is
port( clkin : in std_logic;
dip : in std_logic_vector(1 downto 0);
money : out std_logic_vector(9 downto 0));
end entity;
architecture behav of count_money is
signal qibu : std_logic_vector(9 downto 0);
signal temp0,temp1 : std_logic_vector(9 downto 0);
begin
with dip select
qibu <= conv_std_logic_vector(5,10) when "00",
conv_std_logic_vector(6,10) when "01",
conv_std_logic_vector(8,10) when "10",
conv_std_logic_vector(10,10) when "11";
process(clkin,temp0,temp1)
begin
if rising_edge(clkin) then
temp0<=temp0+'1';
end if;
end process;
money<=qibu when temp0<=qibu else temp0;
end behav;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -