代码搜索：Loop

找到约 10,000 项符合「Loop」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/267888/6478148

m mmse_ic_mldetection_4x2.m

function [DemapSymbol_1,DemapSymbol_2,DemapSymbol_3,DemapSymbol_4] ... =mmse_IC_mlDetection_4x2(ChFR11,ChFR21,ChFR31,ChFR41,ChFR12,ChFR22,ChFR32,ChFR42,R1_S1,R1_S2,R2_S1,R2_S2,NoisePwr,qam)
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www.eeworm.com/read/488265/6490148

asm counter design.asm

ORG 0 MOV TMOD,#00000101B ;置T0计数器方式1 MOV TH0,#0 ;置T0初值 MOV TL0,#0 SETB TR0 ;T0运行 LOOP: MOV P1,TL0 ;记录P1口脉冲个数 LJMP LOOP ;返回 END
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www.eeworm.com/read/488265/6490685

asm port1 (1).asm

ORG 00H LOOP: MOV A, #0FEH ;赋初值 MOV R2, #8 ;设计数值 OUTPUT: MOV P1, A ;送P1口输出 RL A ;数据移位 ACALL DELAY
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www.eeworm.com/read/488265/6490821

lst serial to parallel.lst

A51 MACRO ASSEMBLER SERIAL_TO_PARALLEL 07/31/2006 08:46:15 PAGE 1 MACRO ASSEMBLER A51 V8.00 OBJECT MODULE PLACED IN Serial to Parallel.OBJ
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www.eeworm.com/read/488200/6497738

s pivec.s

; :ts=8 include asmglobal.h extrn Stktop,Spsave,Sssave,piint:proc,doret:proc,eoi:proc DMAEN equ 4 .DATA public acc_delay acc_delay dw 0 .CODE dbase dw @Data ; save loc for ds (m
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vhd t51.vhd

-- -- This file tests support for the synthesis of While condition when evaluated as a constant. -- entity TEST is port (A : in bit_vector (7 downto 0); B : in bit; Z : out bit_
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www.eeworm.com/read/487590/6506042

vhd t101.vhd

-- -- This file tests support for user defined functions. -- entity TEST is port( A : in bit_vector(0 to 3); Z : out bit); end TEST; architecture T101 of TEST is function parity(A
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vhd t191.vhd

-- -- This example represents a 64 bit parity generator. The following code -- implies a 64 * (xor time unit) delay due to its structure based on a single -- for loop. The test case t192.vhd illust
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www.eeworm.com/read/487590/6506053

vhd t102.vhd

-- -- This file tests Support for user defined procedures. -- entity TEST is port( A : in bit_vector(0 to 3); Z : out bit); end TEST; architecture T102 of TEST is procedure parity
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www.eeworm.com/read/487590/6506058

vhd t81.vhd

-- -- This file tests support for Pre-defined attributes -- entity TEST is port( A : in bit_vector(0 to 3); Z : out bit); end TEST; architecture T81 of TEST is begin process (A)
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