t102.vhd

Workshop vhdl code from Esperan

--
-- This file tests Support for user defined procedures.
--
entity TEST is 
	port( A : in  bit_vector(0 to 3);
	      Z : out bit);
end TEST;

architecture T102 of TEST is
	procedure parity(A: in bit_vector; signal Z: out bit)  is
		variable TMP : bit;
	begin
		TMP:= '0';
			for I in A'range loop
				TMP:=TMP xor A(I);
			end loop;
		Z <= TMP;
	end parity;
begin
	parity(A, Z);
end T102;