t81.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 29 行

--
-- This file tests support for Pre-defined attributes
--
entity TEST is 
	port( A : in  bit_vector(0 to 3);
	      Z : out bit);
end TEST;

architecture T81 of TEST is
begin
	process (A)
		variable TMP_A : bit_vector(A'length -1 downto 0);
		variable TMP : bit;
	begin
		TMP_A(A'high downto A'low) := A; 
		TMP:= '0';
		if A'Left > A'Right then
			for I in A'range loop
				TMP:=TMP xor TMP_A(I);
			end loop;
		else
			for I in A'reverse_range loop
				TMP:=TMP xor A(I);
			end loop;
		end if;
		Z <= TMP;	
	end process;
end T81;