t51.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for the synthesis of While condition when evaluated as a constant.
--
entity TEST is
	port (A : in  bit_vector (7 downto 0);
	      B : in  bit;
	      Z : out bit_vector (7 downto 0));
end TEST;
architecture T51 of TEST is
begin
	process(B, A)
		variable I : integer;
	begin
		I:= 0;
		while (I < 8) loop
			Z(I) <= B and A(i);
			I := I + 1;
		end loop;
	end process;
end T51;