t191.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 23 行

--
-- This example represents a 64 bit parity generator. The following code
-- implies a 64 * (xor time unit) delay due to its structure based on a single
-- for loop. The test case t192.vhd illustrates how the critical path of the 
-- design can be reduced almost by half.
--
entity TEST is
	port( A : in  bit_vector(63 downto 0);
	      Z : out bit);
end TEST;
architecture T191 of TEST is
begin
	process(A)
		variable TMP: bit;
	begin
		TMP := '0';
		for I in A'range loop
			TMP := TMP xor A(I);
		end loop;
		Z <= TMP;
	end process;
end T191;