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找到约 10,000 项符合
Logic Analyzer 的代码
multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
4选1数据选择器.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_4 IS
PORT(e,d0,d1,d2,d3,d5,d6,d7,d8,a,b:IN STD_LOGIC;
q:OUT STD_LOGIC;
)
END ENTITY mux_4;
ARCHITECTU
3_8译码器.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_3_8 IS
PORT(a,b,c,g1,g2a,g2b:IN STD_LOGIC;
y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); )
END decoder_3_8;
ARCHITECTURE rt1
实验1.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mul_1 IS
PORT(a,b:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY mu1_1;
ARCHITECTURE rt5 OF muL_1 IS
SIGNAL indata:STD_
songer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
clk8HZ:in std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
por
notetabs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of note
ext_32to25.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity EXT_32to25 is
port (
RIGHTOUT: in std_logic_vector (31 downto 0);
SMALLMAN: out std_logic_vector (24 downto 0)
);
ext2_32to25.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity EXT2_32to25 is
port (
LEFTOUT: in std_logic_vector (31 downto 0);
MANSFT: out std_logic_vector (24 downto 0)
);
barrelr.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity BARRELR is
port (
IN0: in std_logic_vector (31 downto 0);
SIGN : in std_logic;
S : in std_logic_vector (4 downto