实验1.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mul_1 IS
PORT(a,b:IN STD_LOGIC;
       q:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY mu1_1;

ARCHITECTURE rt5 OF muL_1 IS
SIGNAL indata:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
    indata<=a&b;
    PROCESS(indata)
       BEGIN
          CASE indata IS
              WHEN "00"=>q<="010101";
              WHEN "01"=>q<="011010";
              WHEN "10"=>q<="011010";
              WHEN "11"=>q<="101001";
        END CASE;
END PROCESS; 
END ARCHITECTURE rt5;