4选1数据选择器.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_4 IS
PORT(e,d0,d1,d2,d3,d5,d6,d7,d8,a,b:IN STD_LOGIC;
                                 q:OUT STD_LOGIC;
   )

END ENTITY mux_4;
ARCHITECTURE rt2 OF mux_4 IS
SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
     sel<=a&b&e;
       q<=d0 WHEN sel="000" ELSE
          d1 WHEN sel="010" ELSE
          d2 WHEN sel="100" ELSE
          d3 WHEN sel="110" ELSE

          d5 WHEN sel="001" ELSE
          d6 WHEN sel="011" ELSE
          d7 WHEN sel="101" ELSE
          d8 WHEN sel="111" ELSE
          'Z';
END ARCHITECTURE rt2;