songer.vhd

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12MHZ:in std_logic;
	clk8HZ:in std_logic;
	spkout:out std_logic);
end;
architecture one of songer is
component notetabs
port(clk:in std_logic;
	toneindex:out std_logic_vector(3 downto 0));
end component;
component tonetaba
port(index:in std_logic_vector(3 downto 0);
	tone:out std_logic_vector(10 downto 0));
end component;
component speaker
port(clk:in std_logic;
	tone:in std_logic_vector(10 downto 0);
	spks:out std_logic);
end component;
signal tone:std_logic_vector(10 downto 0);
signal toneindex:std_logic_vector(3 downto 0);
begin
u1:notetabs port map(clk=>clk8HZ,toneindex=>toneindex);
u2:tonetaba port map(index=>toneindex,tone=>tone);
u3:speaker port map(clk=>clk12MHZ,tone=>tone,spks=>spkout);
end;