3_8译码器.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_3_8 IS
PORT(a,b,c,g1,g2a,g2b:IN STD_LOGIC;
                    y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); )
END decoder_3_8;

ARCHITECTURE rt1 OF decoder_3_8 IS
SIGNAL indata:STD_LOGIC_VECTOR(2 DOWNTO 0);  
BEGIN
  indata<=c&b&a;
  PROCESS(indata,g1,g2a,g2b)
    BEGIN
      IF(g1='1' and g2a='0' and g2b='0')THEN
       CASE indata IS
            WHEN "000"=>y<="11111110"; 
            WHEN "001"=>y<="11111101";
	    WHEN "010"=>y<="11111011";
            WHEN "011"=>y<="11110111";
            WHEN "100"=>y<="11101111";
            WHEN "101"=>y<="11011111";
            WHEN "110"=>y<="10111111";
            WHEN "111"=>y<="01111111";
            WHEN OTHERS=>Y<="XXXXXXXX";
        END CASE;
      ELSE
          Y<="11111111";
    END PROCESS;
END ARCHITECTURE rt1;