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Logic Analyzer 的代码
hexin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hexin is
port(bego,over,left,right,cp,clear:in std_logic;
bahe.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bahe is
port(bego,left,right,cp,clear:in std_logic;--CP 接q18脚
q:inout std_logic_ve
yima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(a,b,c,d:in std_logic;
y: inout std_logic_vector(14 downto 0));
end yima;
architecture one of yima is
signal indat
duolufuyong.vhd
library ieee;
use ieee.std_logic_1164.all;
entity duolufuyong is
port(sa,sb:in std_logic;
a,b:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end duolufuy
qiduanyima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity qiduanyima is
port(a,b,c,d:in std_logic;
y:out std_logic_vector(6 downto 0));
end qiduanyima;
architecture one of qiduanyima is
select_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity select_2 is
port(a,b,s:in std_logic;
q:out std_logic);
end;
architecture one of select_2 is
begin
q
vhdl code1.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1
vhdl code7.bak
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
vhdl code7.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
vhdl code8.bak
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;architecture archi