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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock is port(clk,clk2:in std_logic; show:out std_logic_vector(6 downt

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yima is port(kin3,kin2,kin1,kin0:in std_logic; sel2,sel1,sel0:in std_logic; Y:out std_l

library ieee; use ieee.std_logic_1164.all; entity ywjcq is port(clk,load:in std_logic; y:in std_logic_vector(6 downto 0); dout:buffer std_logic_vector(6 downto 0)); end ywjcq; archite

--clk 10ns --clk2 20ns library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FourToEight is port ( clk: IN STD_LOGIC;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CODER138 IS PORT (en1:IN STD_LOGIC; en2:IN STD_LOGIC; en3:IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(2 DOWNTO 0); co: OUT

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity McuToFpga is generic(QWidth : Integer := 24); --移位寄存器的宽度 port( CLK: in std_logic; --同步时钟,上升研写入数据 DA

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dds is port( frep: in std_logic_vector(14 downto 0); phase: in std_logic_vector(8 downto 0);

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity caideng is port(clk:in std_logic; ledout:out std_logic_vector(0 to 9)); end caideng; architectur

library ieee; use ieee.std_logic_1164.all; entity reg32bit is port(load:in std_logic; din:in std_logic_vector(31 downto 0); dout:out std_logic_vector(31 downto 0)); end reg32bit; archit

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mul16 is port (clk:in std_logic; a,b:in std_logic_vector(15 downto 0); q:ou