📄 ywjcq.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity ywjcq is
port(clk,load:in std_logic;
y:in std_logic_vector(6 downto 0);
dout:buffer std_logic_vector(6 downto 0));
end ywjcq;
architecture bb of ywjcq is
begin
process(clk,load)
begin
if load='1' then
dout<=y;
elsif clk'event and clk='1' then
dout<=dout(0)&dout(6 downto 1);
end if;
end process;
end bb;
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