coder138.vhd

来自「用vhdl 语言实现138译码器」· VHDL 代码 · 共 33 行

LIBRARY  IEEE;  
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY CODER138 IS 
PORT (en1:IN STD_LOGIC;
      en2:IN STD_LOGIC;
      en3:IN STD_LOGIC;
      a: IN STD_LOGIC_VECTOR(2 DOWNTO 0); 
    co: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  
END CODER138;     
ARCHITECTURE behav OF CODER138  IS 
SIGNAL en:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
 en<=en1 & en2 & en3;
 PROCESS(a,en)
BEGIN
 IF en="111" then
  CASE a IS
    WHEN "000" => co<="11111110" ;
    WHEN "001" => co<="11111101" ;
    WHEN "010" => co<="11111011" ;
    WHEN "011" => co<="11110111" ;
    WHEN "100" => co<="11101111" ;
    WHEN "101" => co<="11011111" ;
    WHEN "110" => co<="10111111" ;
    WHEN "111" => co<="01111111";
    WHEN OTHERS => NULL ;
   END CASE;
 else
    co<="11111111";
  END IF;
 END PROCESS; 
END ARCHITECTURE behav ;