48_4.12.txt

网络通信中的MII接口 通常将4位nibble数据送出

--clk 10ns
--clk2 20ns





library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity FourToEight is
port (
clk: IN STD_LOGIC; --RXC
clk2: IN STD_LOGIC;--data_out Clk
reset: in bit;
RXDV: IN STD_LOGIC;
RXER: IN STD_LOGIC;
RXD: in STD_LOGIC_VECTOR (3 DOWNTO 0) ; 
Frame_vaild: buffer STD_LOGIC;
CRS: in std_logic;
data_out: out STD_LOGIC_VECTOR (7 DOWNTO 0) ); 
end FourToEight;

architecture Behavioral of FourToEight is
signal tempR1 : STD_LOGIC_VECTOR(3 Downto 0);
signal tempR2 : STD_LOGIC_VECTOR(3 Downto 0);
signal tempR3 : STD_LOGIC_VECTOR(7 Downto 0);
signal tempR4 : STD_LOGIC_VECTOR(7 Downto 0);
signal tempR5 : STD_LOGIC_VECTOR(7 Downto 0);
signal Q : STD_LOGIC_VECTOR(7 Downto 0);
signal count : STD_LOGIC:='0';
shared variable CNT : integer:=0 ;
--shared variable Frame_count: integer:=0;---帧计数
begin


process(clk, reset)  --合成时钟计数
begin
if (reset = '0') then
  count<= '0';
elsif (clk'event and clk ='1') then
  count <= not count;
end if;
end process;

process(clk, reset)  --合成时钟计数
begin
if (reset = '0' or CNT =10000) then
  CNT :=0;
elsif (clk'event and clk ='1') then
  CNT := CNT+1;
end if;
end process;

process(RXDV,RXER,reset,Frame_vaild,clk,RXD,tempR1,tempR2,tempR3)
begin
if(reset='0') then
tempR1 <= (others => '0');
tempR2 <= (others => '0'); 
Frame_vaild<='0';
--Frame_count:=0;
elsif (clk'event and clk ='1') then
if RXDV='1' and RXER='0' then
   if ( count  = '0') then
   tempR1 <= RXD;
   else
   tempR2 <= RXD;
end if ;
end if;
--end if;
if RXDV='0' and RXER='0' then
Frame_vaild<='1';
--Frame_count:=Frame_count+1;
end if;
if RXDV='0' and RXER='1' then
tempR1 <= (others => '0');
tempR2 <= (others => '0');
end  if;
if RXDV='1' and RXER='1' then
tempR1 <= (others => '0');
tempR2 <= (others => '0');
end  if;
end if;
end  process;



process(clk2,reset)
begin
if reset='0' then
tempR3 <= (others => '0');
else if(clk2'event and clk2='1')then
tempR3 <=tempR1&tempR2;
end if;
end if;
end process;







process(CRS,tempR3)
begin
if CRS='0' then
tempR4<=tempR3;
else if CNT=10000 then
tempR4<=tempR3;
end if;
end if;
end process;


process(clk2)
begin
 if(clk2'event and clk2='1' )then
tempR5<=tempR4;
end if;

end process;




data_out <=tempR5;
end Behavioral;





4.12第二版 改进点 仿真还是有错误

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity SPI is
PORT (
          SPIC     : IN  std_logic;
          SPIS_N   : buffer  std_logic;
          SPID     : OUT std_logic;
		  SPIQ     : in  std_logic;
		  temp_SPIQ: out std_logic_vector(7 downto 0);
		  PS0      : out std_logic; --pin114=0
		  PS1      : out std_logic; --pin113=1  SPI模式
          RST      : in  std_logic);
end SPI;

architecture bev of SPI IS
	
		shared variable count: integer range 0 to 23 ;
        signal temp : std_logic_vector(23 downto 0):= x"0038C0";--"0011100011000000"
 --       signal temp1 : std_logic_vector(7 downto 0):="00000011";
		--signal temp_SPIQ:std_logic_vector(7 downto 0);
begin
        
     	PS0<='0';
		PS1<='1';
process (SPIC,SPIS_N,RST)
begin
        if (RST='0') then
               ---------输入执行语句**
				SPIS_N<='0';
        elsif (SPIC'event and SPIC='0') then
                if (SPIS_N='0') then
                        temp<= temp(0)&temp(23 downto 1); 
						if count =23 then 
				SPIS_N<='1';
                end if;
        end if;
end if;
end process;

process (RST,SPIC)
begin
if(RST='0') then
count := 0;
elsif SPIC'event and SPIC='0' then
count := count +1;-- right shift
end if;
end process;

process (SPIQ,SPIC) --将SPIQ进来的寄存器数据分配到各个引脚上  用于测试
begin
if(RST='0') then
temp_SPIQ<=(others=>'0');
elsif SPIC'event and SPIC='0' then 
--if temp1(7 downto 0)="00000011" then
--if count>15 and count<24  then
if count=16 then
temp_SPIQ(0)<=SPIQ;
elsif count=17 then
temp_SPIQ(1)<=SPIQ;
elsif count=18 then
temp_SPIQ(2)<=SPIQ;
elsif count=19 then
temp_SPIQ(3)<=SPIQ;
elsif count=20 then
temp_SPIQ(4)<=SPIQ;
elsif count=21 then
temp_SPIQ(5)<=SPIQ;
elsif count=22 then
temp_SPIQ(6)<=SPIQ;
elsif count=23 then
temp_SPIQ(7)<=SPIQ;

end if;
end if;
--end if;
--end if;
--end if;
--end if;
--end if;
--end if;
--end if;
--end if;
--end if;
--end if;
end process;

SPID <= temp(0);
end bev;