caideng.vhd

来自「设计一个彩灯控制器」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity caideng  is
    port(clk:in std_logic;
         ledout:out std_logic_vector(0 to 9));
end caideng;
architecture rtl of caideng is
   signal cnt:std_logic_vector(3 downto 0);
begin
   process(clk)
   begin
    	if(clk'event and clk='1')then
           If cnt="1001"then 
               cnt<="0000";
           else		
               cnt<=cnt +"1";
           End if;
        End if;
   End process;
   With cnt Select
   ledout<= "1000000000" when  "0000",
        "0100000000" when "0001",
        "0010000000" when "0010",
	    "0001000000" when "0011",
        "0000100000" when "0100",
        "0000010000" when "0101",
	    "0000001000" when "0110",
        "0000000100" when "0111",
	    "0000000010" when "1000",
        "0000000001" when others;
 end rtl;