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找到约 10,000 项符合
Logic Analyzer 的代码
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
mux21s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX21S IS
PORT (S : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q
reg1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg1 is
port(d: in std_logic_vector(31 downto 0);
clk:in std_logic;
q:out std_logic_vector(31 downto 0));
end entity reg1;
a
adder32.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32 is
port(n: in std_logic_vector(31 downto 0);
a: in std_logic_vector(31 downto 0);
cl
reg2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg2 is
port(e: in std_logic_vector(31 downto 0);
clk:in std_logic;
p:out std_logic_vector(31 downto 0));
end entity reg2;
a