mux21s.vhd

来自「Alera 的8051 IP core的示例文件5个」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX21S IS
    PORT (S : IN STD_LOGIC;
          A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
          B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
       QOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  
        );
END MUX21S;
ARCHITECTURE behav OF MUX21S IS
  BEGIN
  PROCESS (S)  
     BEGIN
        IF S = '1' THEN QOUT<=A;
        ELSE QOUT<=B ; END IF;
  END PROCESS;
END behav;