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找到约 10,000 项符合
Logic Analyzer 的代码
fenpinqi.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE8 IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT
pulse8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE8 IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT
andarith.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity andarith is
port(abin:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(7 downto 0
clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk,clk2:in std_logic;
show:out std_logic_vector(6 downt
tran.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tran13to16 is
port(
a13,b13: in std_logic_vector(12 downto 0);
clk:
register16.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity register15 is
port(
Din: in std_logic_vector(15 downto 0);
clk:
rightshift.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity rightshift is
port(
Din: in std_logic_vector(15 downto 0);
clk:
fred.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY fred IS
PORT
(
clk : IN STD_LOGIC;
num : in STD_LOGIC_VECTOR(3 DOWNTO 0
segment7.vhd
---------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
---------------------------------------
ENTITY segment7 IS
PORT (CLK: IN STD_
insertb.vhd
--输出端用“11”表示符号“V”，“01”表示“1”码， “00”表示“0”码，“10”表示符号“B”。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity insertb is
port( clk : in std_logic;
co