tran.vhd

来自「采用加法树流水线乘法构造八位乘法器」· VHDL 代码 · 共 27 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity tran13to16 is 
	port(
		a13,b13:		in std_logic_vector(12 downto 0);
		clk:        in std_logic;
		a16,b16:		out std_logic_vector(15 downto 0));
end entity tran13to16;

architecture beha of tran13to16 is
signal  a:std_logic_vector(15 downto 0);
signal  b:std_logic_vector(16 downto 0);
begin
a16<=a;
b16[15:0]<=b[16:1];
process(clk)
		begin	
		if(rising_edge(clk)) then
	           a<="000"&a13;
	           b<=b13&"0000";
	end if;
end process;
end beha;