register16.vhd

来自「采用加法树流水线乘法构造八位乘法器」· VHDL 代码 · 共 21 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity register15 is 
	port(
		Din:		in std_logic_vector(15 downto 0);
		clk:        in std_logic;
		Dout:		out std_logic_vector(15 downto 0));
end entity register15;

architecture beha of register15 is
begin
process(clk)
		begin	
		if(rising_edge(clk)) then
	           Dout<=Din;
	    end if;
end process;
end beha;