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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY comclk IS PORT( sel: IN STD_LOGIC_VECTOR(2 downto 0); clk:in std_logic;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ymdhms is port( setn:std_logic_vector(5 downto 0); ena,clk:in std_logic; cosecond: out std_logic; y

--file usbf_pd.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity usbf_pd is generic ( usbf_t_pid_out : std_logic_vector

--the rs232 send module --include one clk and one send component library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; entity rs232_t is --send and pll1的物理连接 p

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --synopsys translate_off library UNISIM; use UNISIM.Vcomponents.all; --synopsys translate_on entity pcore is port ( clk: i

-- ================================================================================ -- (c) 2007 Altera Corporation. All rights reserved. -- Altera products are protected under numerous U.S. and fore

-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: cp_mem.vhd

-- megafunction wizard: %FFT v7.1% -- GENERATION: XML -- ============================================================ -- Megafunction Name(s): -- auk_dspip_r22sdf_top_fft_71 -- =============

-- Generated Binary Up Counter -- The first design entity is a T-type flip-flop. -- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce

--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity i60bcd i