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Logic Analyzer 的代码
bingzhuanchuan.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity bingzhuanchuan is
Port (cp:in std_logic;
cs:in std_logic;
datain:in s
cnt30.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt30 is
port(clk5,enat:in std_logic;
d:out std_logic_vector(4 downto 0);
cout3:out
cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(ena,clk3,lock:in std_logic;
c:out std_logic_vector(3 downto 0);
cout2:out std_
seltime.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SELTIME IS
PORT(
CLK:IN STD_LOGIC;
SEC1,SEC0,MIN1,MIN0,H1,H0:I
second.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SECOND IS
PORT(CLK,RESET:IN STD_LOGIC;----时钟/清零信号
SECOND0,SECOND1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);----秒高位/
minute.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MINUTE IS
PORT(CLK,RESET:IN STD_LOGIC;
MIN1,MIN0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC
control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
sram.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************
frequency.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************
flash.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************