bingzhuanchuan.vhd

来自「这是一个用VHDL语言编写的并口转串口程序」· VHDL 代码 · 共 57 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity bingzhuanchuan is 
Port (cp:in std_logic;
     cs:in std_logic;
     datain:in std_logic_vector(15 downto 0);
     output:out std_logic);
end bingzhuanchuan;
Architecture a of bingzhuanchuan is
signal cnt:std_logic_vector(3 downto 0);
signal z:std_logic;
begin
process(cp)
begin
if cs='1' then  
  cnt<="0000";
elsif cp'event and cp='0' then 
 if cnt="1111" then
   cnt<="0000";
 else
   cnt<=cnt+1;
  end if;
end if;
end process;
process(cnt)
begin
case cnt is
when "0000"=>z<=datain(15);
when "0001"=>z<=datain(14);
when "0010"=>z<=datain(13);
when "0011"=>z<=datain(12);
when "0100"=>z<=datain(11);
when "0101"=>z<=datain(10);
when "0110"=>z<=datain(9);
when "0111"=>z<=datain(8);
when "1000"=>z<=datain(7);
when "1001"=>z<=datain(6);
when "1010"=>z<=datain(5);
when "1011"=>z<=datain(4);
when "1100"=>z<=datain(3);
when "1101"=>z<=datain(2);
when "1110"=>z<=datain(1);
when others=>z<=datain(0);
end case;
end process;
process(cp,z)
begin
if cp'event and cp='0' then
output<=z;
end if;
end process;
end a;