📄 minute.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MINUTE IS
PORT(CLK,RESET:IN STD_LOGIC;
MIN1,MIN0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END MINUTE;
ARCHITECTURE MIN OF MINUTE IS
BEGIN
PROCESS(CLK)
VARIABLE CNT1,CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RESET='1' THEN----当CKR为1时,高低位均为0
CNT1:="0000";
CNT0:="0000";
ELSIF CLK'EVENT AND CLK='1' THEN
IF CNT1="0101" AND CNT0="1000" THEN
COUT<='1';
CNT0:="1001";
ELSIF CNT0<"1001" THEN
CNT0:=CNT0+1;
ELSE
CNT0:="0000";
IF CNT1<"0101" THEN
CNT1:=CNT1+1;
ELSE
CNT1:="0000";
COUT<='0';
END IF;
END IF;
END IF;
MIN1<=CNT1;
MIN0<=CNT0;
END PROCESS;
END MIN;
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