cnt10.vhd

来自「实现电子密码锁的各项功能,经过编译和仿真」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(ena,clk3,lock:in std_logic;
           c:out std_logic_vector(3 downto 0);
        cout2:out std_logic);
end cnt10;
architecture five of cnt10 is 
  signal c_temp:std_logic_vector(3 downto 0);
  signal cout2_temp:std_logic;
      begin 
           process(clk3)
             begin              
                if clk3'event and clk3='1' then 
                 if ena='1' then
					if lock='1' then
                   if c_temp="1001" then 
                      c_temp<="0000";
                      cout2_temp<='1'; 
                      else
                     c_temp<=c_temp+1;
                     cout2_temp<='0';
                   end if;
					else cout2_temp<='0';
						c_temp<="0000";
					end if;
                 end if;
               end if;
              c<=c_temp;
              cout2<=cout2_temp;
              end process;
       end five;