📄 cnt30.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt30 is
port(clk5,enat:in std_logic;
d:out std_logic_vector(4 downto 0);
cout3:out std_logic);
end cnt30;
architecture six of cnt30 is
signal cout3_temp:std_logic;
signal d_temp:std_logic_vector(4 downto 0);
begin
process(clk5)
begin
if clk5'event and clk5='1'then
if enat='1' then
if d_temp<"11110" then
d_temp<=d_temp+1;
cout3<='1';
else cout3<='0';
end if;
end if;
end if;
d<=d_temp;
end process;
end six;
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