reg1.vhd

来自「实现电子密码锁的各项功能,经过编译和仿真」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
entity Reg1 is
    port(q: in std_logic_vector(7 downto 0);
       clk1:in std_logic;
        a:out std_logic_vector(7 downto 0));
    end Reg1;
   architecture one of Reg1 is
         begin 
           process(clk1)
             begin 
               if clk1'event and clk1='1' then 
                     a<=q;
               end if;
            end process;
     end one;