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找到约 10,000 项符合
Logic Analyzer 的代码
main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity main is
port(clk1:in std_logic;
leda1,leda10a,ledb1,ledb10b:out std_logic_vect
minute0.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY minute0 IS
PORT(
en : IN STD_LOGIC;
min1,min0 :out std_logic_vector(3 downto 0);
co
ahour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ahour is
port(en,mode :in std_logic;
h1,h0 :out std_logic_vector(3 downto 0));
end ahour;
archi
clock.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
reset :
mul16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port(clk:in std_logic;
a:in std_logic_vector(15 downto 0);
b:i
mul16.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port(clk:in std_logic;
a:in std_logic_vector(15 downto 0);
b:i
xianshi.vhd
--XIANSHI
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XIANSHI IS
PORT( CLK0 : IN STD_LOGIC;
SEC_L,SEC_H,MIN_L,MIN_H : IN STD_LOGIC_VECTOR(6 DOWN
dcnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA: IN STD_LOGIC;
DATAIN:IN STD
dcnt10.vhd
--DCNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT10 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA: IN STD_LOGIC;
jsq.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY JSQ IS PORT(
COOK : IN STD_LOGIC;
DATA3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0