jsq.vhd

来自「eda微波炉程序控制器 初学vhdl语言的控制程序设计」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY JSQ IS  PORT(
   COOK  : IN STD_LOGIC;
   DATA3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
   LOAD  : IN STD_LOGIC;
   CLK   : IN STD_LOGIC;
   SEC_L : OUT STD_LOGIC_VECTOR(3 TO 0);
   SEC_H : OUT STD_LOGIC_VECTOR(3 TO 0);
   MIN_L : OUT STD_LOGIC_VECTOR(3 TO 0);
   MIN_H : OUT STD_LOGIC_VECTOR(3 TO 0);
   DONE  : OUT STD_LOGIC);
END JSQ;

ARCHITECTURE ART OF JSQ IS
  COMPONENT DCNT10 IS
     PORT(CLK,LOAD,ENA : IN STD_LOGIC;
                DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                    CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             CARRY_OUT : OUT STD_LOGIC);
  END COMPONENT DCNT10;
  COMPONENT DCNT6 IS
     PORT(CLK,LOAD,ENA : IN STD_LOGIC;
                DATAIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                    CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             CARRY_OUT : OUT STD_LOGIC);
  END COMPONENT DCNT6;

         SIGNAL NEWCLK : STD_LOGIC;
         SIGNAL S1 : STD_LOGIC;
         SIGNAL S2 : STD_LOGIC;
         SIGNAL S3 : STD_LOGIC;
         SIGNAL S4 : STD_LOGIC;
   BEGIN
      U1:DCNT10 PORT MAP(CLK,LOAD,COOK,DATA3(3 DOWNTO 0),SEC_L,S1);
      U2:DCNT6  PORT MAP(S1,LOAD,COOK,DATA3(7 DOWNTO 4),SEC_H,S2);
      U3:DCNT10 PORT MAP(S2,LOAD,COOK,DATA3(11 DOWNTO 8),MIN_L,S3);
      U4:DCNT6  PORT MAP(S3,LOAD,COOK,DATA3(15 DOWNTO 12),MIN_H,S4);
      DONE<=S1 AND S2 AND S3 AND S4;
END ARCHITECTURE ART;