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Logic Analyzer 的代码
seven.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY seven IS
PORT
( men: IN std_logic_vector(6 downto 0);
pass: buffer std_logic
);
END seven;
ARCHITECTURE beha
shizhong.txt
1. 10进制计数器设计与仿真
（1）10进制计数器VHDL程序
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.
dianziqin.txt
1.顶层程序与仿真
（1）顶层VHDL程序
--文件名：top.vhd
--功能：顶层文件
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port
saomiao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiao is
port(one,ten:in std_logic_vector(3 downto 0);
clk:in std_logic;---1khz;
data:out
cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk: in std_logic;
cout: out std_logic);
end cnt10;
architecture behav of cnt10 is
begin
alaw_nl_l.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alaw_nl_l is
port(
data :in std_logic; --pcm signal a
clock :in std_logic; --clock signal
framea :in std_logic
uart.vhd
--/*******************************************************************
-- *
-- * DESCRIPTION: UART top level module implements full duplex UART function.
-- *
-- * AUTHOR: Jim Jian
-- *
-
genxlib_arch.vhd
--------------------------------------------------------------------------------
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- infor
lifttt.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lift is
port (
clkin:in STD_LOGIC;
upin:in STD_LOGIC;
downin:in STD_LOGIC;
st_ch:in STD_LOGIC;
lifttt.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lift is
port (
clkin:in STD_LOGIC;
upin:in STD_LOGIC;
downin:in STD_LOGIC;
st_ch:in STD_LOGIC;